31st Annual International Symposium on Computer Architecture
Although these cases are rare, we obtained the best results by generating a critique using the future bits that were ... We scaled up the instruction window size (and associated buffers, the scheduling window and load/store buffers) by a ... Perceptron [32, 16]: Perceptron prediction is a two- level scheme using perceptrons instead of two-bit counters as the ... 2 fp Hardware Daia Prefetcher Stream-based ( 1 6 streams) Instruction Cache 64 KB, 8-way, 64-byte line LI Data Cache 32 KB.
| Title | : | 31st Annual International Symposium on Computer Architecture |
| Author | : | IEEE Computer Society. Technical Committee on Computer Architecture |
| Publisher | : | - 2004 |
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